In semiconductor technology, an integrated circuit pattern can be formed on a substrate using various processes including a photolithography process, ion implantation, deposition and etch. Damascene processes are utilized to form multilayer copper interconnections including vertical interconnection vias and horizontal interconnection metal lines. During a damascene process, trenches are formed in a dielectric material layer, metal such as copper or tungsten is filled in the trenches, then a chemical mechanical polishing (CMP) process is applied to remove excess metal on the dielectric material layer and planarize the top surface.
As the integrated circuit (IC) fabrication moves to advanced technology nodes, the IC feature size scales down to smaller dimensions. For example, the trench dimensions get smaller and smaller and as a result filling the metal layer in the trench becomes increasingly difficult. Oftentimes, a void, seam, or pit is formed after the metal layer is deposited. The poor step coverage of the barrier/adhesion layer and the metal layer, the small feature size of the trench opening, and the high aspect ratio of the opening all can contribute to the formation of voids. Voids in the metal film can trap impurities inside and can be opened up during the planarization process after the metal film deposition. A buried void or a void that is opened can degrade device yield and cause reliability problems, such as delamination and electro-migration during reliability testing. Moreover, a subsequent interconnect feature, such as a metal line that lands on and makes electrical contact with the underlying metal film having a void therein can degrade device performance and cause reliability problems.
Accordingly, a structure and method for forming an interconnect structure are needed to address the above issues.